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Bit
31:0
Name
WDATA
Reset
0x00000000
Access
RW
Description
Write Data
The data to be written to the address in MSC_ADDR. This register must be written when the WDATAREADY bit of MSC_STATUS
is set, otherwise the data is ignored.
7.5.7 MSC_STATUS - Status Register
Offset
0x01C
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5
ERASEABORTED
0
R
The Current Flash Erase Operation Aborted
When set, the current erase operation was aborted by interrupt.
4
WORDTIMEOUT
0
R
Flash Write Word Timeout
When this bit is set, MSC_WDATA was not written within the timeout. The flash write operation timed out and access to the
flash is returned to the AHB interface. This bit is cleared when the ERASEPAGE, WRITETRIG or WRITEONCE commands in
MSC_WRITECMD are triggered.
3
WDATAREADY
1
R
WDATA Write Ready
When this bit is set, the content of MSC_WDATA is read by MSC Flash Write Controller and the register may be updated with the
next 32-bit word to be written to flash. This bit is cleared when writing to MSC_WDATA.
2
INVADDR
0
R
Invalid Write Address or Erase Page
Set when software attempts to load an invalid (unmapped) address into ADDR
1
LOCKED
0
R
Access Locked
When set, the last erase or write is aborted due to erase/write access constraints
0
BUSY
0
R
Erase/Write Busy
When set, an erase or write operation is in progress and new commands are ignored
7.5.8 MSC_IF - Interrupt Flag Register
Offset
0x02C
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2011-04-12 - d0001_Rev1.10
35
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